To enable acquisition of a base station by a mobile terminal included in a telecommunications system based upon the standard 3GPP FDD mode, TDD mode, etc., the corresponding receiver needs to perform frame synchronization and identification of the so-called codegroup. These functions are important for the execution of the subsequent steps of the cell search system.
In particular, when a mobile terminal is turned on, it does not have any knowledge of the timing of the transmitting cell to which it is to be assigned. The 3GPP standard proposes an initial cell search procedure for acquiring the cell signal and synchronizing therewith. This synchronization procedure basically includes three steps: (1) slot synchronization; (2) frame synchronization and identification of the codegroup, i.e., the group of cell codes; and (3) identification of the scrambling code.
In the implementation of the second step, it is assumed that the slot synchronization has previously been obtained during the first step. At this point, to obtain the frame synchronization and identify the codegroup (to which the offset of the cell is associated), in the second step the Secondary Synchronization Channel (SSCH) is used. More particularly, codes or words of 256 chips (i.e., letters) are transmitted at the beginning of each slot.
The sixteen 256-chip complex codes used by the standard are generated as follows. A first sequence at chip rate b having a repetition period of 16 (i.e., repeating every 16 elements) is multiplied by a sequence·16 times slower according to the following two formulas to obtain the base sequence z, where:z=<b, b, b, −b, b, b, −b, −b, b, −b, b, −b, −b, −b, −b, −b>; andb=<1, 1, 1, 1, 1, 1, −1, −1, −1, 1, −1, 1, −1, 1, 1, −1>.
The base sequence z is then multiplied element by element by a Hadamard code of length 256 chosen according to the following rule. If m is the number identifying the Secondary Synchronization Code (SSC) to be generated, the number of the Hadamard code to be multiplied by the sequence z is equal to 16×(m−1), with m ranging from 1 to 16. Generation of the synchronization codes SSC for the TDD mode is similar to the one used for the FDD mode, with the difference being that, in the former case, just twelve of the sixteen codes SSC are used.
Moreover, the FDD mode and TDD mode differ from one another with respect to the way in which the codegroups are associated with the contents of the secondary synchronization channel SSCH. In the FDD mode, on the secondary synchronization channel SSCH a code SSC is sent for each slot, in 15 consecutive slots. There are 64 possible sequences indicated by the standard, which belong to a Reed-Solomon code defined therein. Each sequence identifies a group of eight primary scrambling codes, among which the aforementioned third step of the cell search procedure will identify the code of the cell onto which the first two steps of the procedure have locked.
In the TDD mode, each slot containing the channel SCCH contains three codes SSC. According to the standard, four possible sets of three codes are defined, the combination and the relative phases of which define the codegroups. Each codegroup identifies one slot offset between the start of the slot and the start of the code on the channel SSCH, and four possible basic midambles to each of which is associated a scrambling code. The third step of the cell search procedure defines which midamble is used in the Primary Common-Control Physical Channel (P-CCPCH).
Referring to FIG. 1, a schematic representation of an architecture of a known prior art circuit which implements the first step and second step of the cell search procedure is now described. The received signal r is sent in parallel to a first branch 411, which implements the first step of the cell search procedure, and to a second branch 412, which implements the second step of the cell search procedure. Both the circuits of the first branch 411 and the circuits of the second branch 412 operate under the control of a controller, designated by 403, which receives the results of their processing operations.
The first branch 411 includes a matched filter 401 for carrying out the correlation on the Primary Synchronization Channel (PSC), setting the channel in correlation with a sequence SG structured as a first hierarchical Golay sequence. A subsequent block 402 implements the algorithm of the first step of the cell search procedure. The use of Golay sequences to carry out synchronization functions in systems of a spread-spectrum and CDMA type is described, for example, in WO-A-0051392, WO-A-0054424, WO-A-0067404 and WO-A-0067405.
The second branch 412 instead includes a correlation section 404, which operates on the secondary codes SSC. The correlation section 404 is followed by a block 405 which implements the algorithm of the second step of the cell search procedure. Operation of the correlation section 404 is enabled by an appropriate enabling signal EN issued by the controller 403.
Since the circuits that implement the second step of the cell search procedure for the FDD mode identify the individual chip, they are of the type illustrated schematically in FIG. 2, which are described in European patent application EP02425619.0, which is assigned to the Assignee of the present application. These circuits include, at the input, a correlation section including a bank of correlators 10, the outputs of which supply the energies corresponding to the individual chips.
After a possible masking with appropriate weights at block 12, the energies are added in a node 14 and are then stored in a bank of registers 16. Each row of registers 16 represents one of the words of the code that is to be recognized, while the columns represent the possible frame starting points in terms of slots, i.e., 15 possible starting points. A block 18 includes a comparator which enables the search for the maximum value to be carried out on the bank 16. The reason for this is to define both the codegroup CD used by the cell being currently evaluated, and the start of the frame expressed as frame offset OF transmitted by the cell itself. In other words, the frame offset OF is a quantity identifying the frame synchronization with reference to the slot timing obtained in the first step, which is not specifically shown for clarity of illustration.
Accordingly, the circuit illustrated in FIG. 2 essentially uses a bank of correlators in parallel or, alternatively, a bank which performs the fast Hadamard transform, for carrying out correlation. As note above, in the TDD mode the second step of the cell search procedure is instead carried out assuming that the position of the synchronization burst, as well as a first slot synchronization, have been acquired and defined in the first step of the cell search procedure. This is done to obtain the following: slot synchronization, by defining the offset between the start of the slot and the position of the synchronization burst therein; codegroup identification; and further information, such as the cell parameter.
To do so, the secondary synchronization channel SSCH is used. In the synchronization slot and simultaneously on the channel PSC are transmitted three 256-chip codes coming from of a set of twelve complex codes, which represents a subset of the secondary synchronization codes SSC used in the FDD mode. To extract all the requisite information from the channel SSCH, it is necessary to correlate the received signal with the possible codes transmitted on the channel SSCH. Of these codes, it is also necessary to identify the set of three codes with the highest correlation energy and to use their phases to define, in accordance with the standard, the corresponding parameters of slot offset (i.e., the distance in time between the start of the slot and the start of the synchronization code), codegroup, and frame number (even or odd frame).
The above operation is carried out by a circuit that includes correlation section including twelve matched filters arranged in parallel. This approach is schematically illustrated in the diagram of FIG. 3, where a bank 20 of twelve complex finite impulse response (FIR) filters, which are coupled to the twelve possible secondary synchronization codes SSC. The samples of the received signal r are sent at the input to the bank 20 of FIR filters. On the twelve outputs of the bank 20, signals indicating the correlation energies corresponding to the codes SSC are generated. These signals are sent to a system 21, for detecting the maximum value.
The system 21 for detecting the maximum value identifies a given number (equal to three) of codes SSC having the highest correlation energy. These codes are sent to a comparison block designated by 22. The block 22 compares the codes with vales in a table. More particularly, the table stores, according to the possible combinations of the phase differences of the set of three codes SSC identified, corresponding codegroups CD, slot offsets OS, and frame numbers FN, which are then supplied at the output by the comparison block 22.
An alternate architecture for implementing the second step of the cell search procedure in the TDD mode is shown in FIG. 4, which is described in detail in Italian patent application T02002A001082, also assigned to the present Assignee. Here, the received signal r is sent at the input to a block 110, which carries out a first correlation operation on a first sequence 16 chips long. The received signal r at output from block 110 is sent to a bank of correlators 111, which forms the correlation section. The samples of the received signal r are also stored in a storage unit 112.
The correlator bank 111 includes only four correlator circuits, one for each code set. The bank 111 receives four “first” codes SSC from a system 113 for generating codes, each one of which belongs to and identifies one of the four possible code sets within the set of codes SSC. There are twelve codes SSC in all, and each code set corresponds to a “first” code identifying the set, and a subset of remaining codes corresponds to the other two codes of the set. The correlation operation performed in block 111 is hence able to supply, at its output, an estimate of the code set received.
In this connection, a block 114 carries out a search for the maximum value received from the correlator bank 111 on the energies corresponding to the first four codes SSC supplied by the system. It also supplies at its output a first code SSC having the best correlation energy, and with the corresponding phase offset. In this way, a code set CS to which the first code SSC belongs is identified.
The first code SSC and its phase offset are to be sent on to a comparison block 115, while the information on the code set is sent to a controller designated by 116. The controller 116 presides over operation of the circuit and, in particular, is designed to supply the code-generation system 113 with the information on the “first” four codes SSC to be generated for identifying the four code sets.
Based upon the first code and the corresponding code set CS identified by the search for the maximum value carried out in the block 114, the controller 116 sends to the code-generation system 113 the information regarding which other codes SSC are to be generated for the correlation operation with the received signal r stored in the storage unit 112. The above other codes are simply the remaining two codes SSC in the subset that completes the code set corresponding to the first code selected by the search carried out by block 114.
Upstream of the bank 111, a multiplexer 120 is provided, which is driven by the controller 116 and selects the output of the block 110 or the output of the storage unit 112 for the bank 111. In this way, the received signal r, in addition to being stored in the unit 112, is initially sent directly to the block 111, where it is correlated with the first four codes that identify the four code sets coming from block 113. Subsequently, once the reference code set has been identified (as a result of the search carried out in the unit 114), the samples of the received signal r stored in the unit 112 can be sent to the block 111 to be correlated with the two remaining codes of the aforesaid code set. The correlator bank 111 is equipped with a correlator memory 121, in which the first code SSC of the detected code set is stored.
Based upon the information regarding the selected code set CS, the controller 116 issues a command to the code-generation system 113. This is done so that the latter will generate the two codes corresponding to the two codes that are missing for composing the set of three codes of the code set CS to make a correlation with the samples of the received signal r stored in the storage unit 112. The result of this correlation operation (which is carried out, so to speak, by “recycling” two of the correlators contained in the bank 111) is also supplied to the block 115, where the set of three codes of the code set CS is recomposed. This set of three codes can be used, together with the corresponding phases, for the comparison with the standard tables to extract the corresponding parameters from the table contained in the comparison block 115.
The prior art approaches illustrated in FIGS. 1-4 thus require allocation of a certain amount of memory and, consequently, of area on the chip. As such, a consequent power consumption for implementing the correlation section for the second step of the cell search procedure results.